1. Field of the Invention
This invention relates to the field of switched-capacitor, differential amplifiers.
2. Background Art
When implementing operational amplifiers in integrated circuits, ideal characteristics are difficult to achieve. Ideally, when a zero voltage is applied between the inputs of an operational amplifier, the output voltage is zero. In actual amplifiers, however, process variations which result in an imperfect matching of components within the amplifier lead to a positive or negative output voltage when the inputs are forced to zero. The magnitude of the output voltage is directly proportional to the open loop gain of the amplifier and is called output offset voltage.
In order to eliminate the effect of offset voltage, a scheme called "auto zeroing" is utilized. In auto zeroing, a two phased switching scheme is used. In one phase, an input voltage V.sub.IN is inputted to one input of an operational amplifier through a capacitor, with the other input being tied to a reference voltage (typically ground). During the second phase, both inputs are tied to ground to compensate for the effect of offset voltage and to automatically "zero" the amplifier. Thus, input voltage signals are only available (valid) during one phase of operation.
It is frequently necessary to design a switched capacitor amplifier circuit whose input is auto zeroed and whose output is continuously valid. In prior art this design requires two amplifier circuits, each with its own set of switches and capacitors.
A typical prior art design of an auto-zero amplifier is illustrated in FIGS. 1A and 1B. FIG. 1A shows a first amplifier which is an auto zeroed structure with gain greater than one and whose output is only available in one phase (AZ* phase). FIG. 1A shows that input voltage V.sub.IN 10 is coupled to capacitor C1 by switch 12 during the AZ* phase, while input voltage V.sub.zero 11 is coupled to capacitor C1 by switch 12 during the AZ phase. Capacitor C1 is also coupled to the negative input of operational amplifier 21 at node 14. Node 14 is also coupled to capacitor C2 as well as coupled to switch 17. Capacitor C2 is coupled to switch 18. During AZ phase, switch 18 is coupled to output reference voltage OUTREF 19, and during AZ* phase, switch 18 is coupled to the output of amplifier 21. Switch 17 is also coupled to the output of amplifier 21 at node 20 during AZ phase. Switch 17 is open circuited during AZ* phase. Reference voltage V.sub.R 15 is coupled to the positive input terminal of amplifier 21.
The circuit of FIG. 1A switches according to control signals AZ and AZ*. These signals represent alternating, non-overlapping timing signals. During the phase when AZ is high (AZ phase), signal V.sub.zero 11 is provided to capacitor C1 which is in turn coupled to the negative input of operational amplifier 21. The output of operational amplifier 21 is coupled to the negative input through switch 17 to provide feedback. Because the input offset of the amplifier is stored during this interval, the amplifier is auto zeroed.
During the phase when AZ* is high (AZ* phase), the direct feedback is cut off and capacitor C2, which had been charged up to the value of the output reference signal 19 plus the amplifier's input offset during the AZ phase, is now connected in a feedback loop. Output voltage V.sub.A at node 20 receives the stored output reference voltage from the capacitor C2. Signal V.sub.IN 10 is provided to capacitor C1, thus causing a potential change at the negative input of the amplifier corresponding to the difference between signal V.sub.zero and V.sub.IN. The potential change at the negative input of the amplifier also causes a potential change at the output of the amplifier at node 20 to keep the voltage across capacitor C2 unchanged. Assuming an ideal operational amplifier and employing node analysis at node 14, the potential at output voltage V.sub.A is given as: ##EQU1## where V.sub.-- =voltage at the negative input of the amplifier.
The valid output for this circuit is available only during the phase when AZ* is high. When AZ is high, the amplifier is auto-zeroed, and the output is equal to the input offset of the amplifier.
This circuit achieves low input offset by storing its offset on capacitor C1 and C2 during AZ phase. If it is desired to generate an output on both phases, a sample and hold circuit must be added such as the one illustrated in FIG. 1B. The circuit of FIG. 1B is a unity gain sample and hold structure. In FIG. 1B, voltage signal V.sub.A at node 20 is coupled to switch 22 during AZ* phase. Switch 22 is also coupled to capacitor C3 at node 23 where output voltage V.sub.OUT is taken from. Capacitor C3 is coupled to the negative input of operational amplifier 26 at node 25. Node 25 is coupled to the output of operational amplifier 26 through switch 27 which is closed during AZ* phase and open during AZ phase. During AZ phase, switch 22 is coupled to the output of operational amplifier 26 at node 28. Reference voltage V.sub.R 15 is coupled to the positive input terminal of operational amplifier 26.
During AZ* phase, switch 22 directly couples valid output voltage V.sub.A to V.sub.OUT at node 23. During this phase, amplifier 26 is auto-zeroed with switch 27 providing direct negative feedback to the negative input terminal of amplifier 26. Also, capacitor C3 is sampling the voltage V.sub.A. During AZ phase, switch 22 is switched from voltage V.sub.A at node 20 to the output voltage of amplifier 26 at node 28. Also, switch 27 is open circuited so that amplifier 26 no longer has direct feedback. Because of the design of the sample and hold circuit of FIG. 1B, the voltage levels at nodes 23 and 25 across capacitor C3 are held to the same values at the beginning of the AZ phase that they are in the AZ* phase. Therefore, output voltage V.sub.OUT at node 23 is still equal to voltage V.sub.A during phase AZ. Each auto-zeroed circuit of FIGS. 1A and 1B has an output that is independent of the operational amplifiers offset. The output offset is not zero, however, due to charge injection from the switches.
Although the combined circuit of FIGS. 1A and 1B illustrate a circuit with an input that is auto-zeroed and an output that is valid on both phases, the circuit has several disadvantages. One drawback is that the prior art circuit requires two separate amplifiers, consuming a larger die area. Another drawback of the prior art circuit is that the circuit exhibits a larger input equivalent offset due to the offset being the sum of two circuit offsets. Furthermore, a glitch appears on the output at the beginning of each clock phase as the amplifier slews from its auto-zeroed voltage to its output voltage.
It is desired to have a circuit that combines both the auto-zeroing and the sample and hold functions. It is also desired to have a circuit that has better immunity to charge injection from the switches. It is further desired to reduce the input offset.